NPN type lateral transistor with minimal substrate operation int

Details NPN type lateral transistor with minimal substrate operation int NPN type lateral transistor with minimal substrate operation int

1987-06-17

1991-06-25

Carroll, J.

357 35, H01L 2972, H01L 2712

Patent

active

050271849

ABSTRACT:
The invention provides a unique sub-micron dimensioned NPN type transistor, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping P+ which is driven in from one side only while N+ is introduced and driven in from both sides, thereby providing an N+ P+P, N+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

REFERENCES:
patent: 4519849 (1985-05-01), Korsh et al.
patent: 4641170 (1987-02-01), Ogura et al.
S. A. Evans et al., "A 1-micron Bipolar VLSI Technology", IEEE Transactions on Electron Devices, vol. ED-27 (Aug. 1980), pp. 1373-1379.
T. Sakai et al., "Gigabit Logic Bipolar Technology: Advanced Super Self-Aligned Process Technology", Electronics Letter, vol. 19, No. 8 (Apr. 14, 1983), pp. 283-284.
S. Konaka et al., "A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology", IEEE Transaction of Electron Devices, vol. ED-33 (Apr. 1986), pp. 526-531.

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