Speedup addressing device by detecting repetitive addressing

Details Speedup addressing device by detecting repetitive addressing Speedup addressing device by detecting repetitive addressing

1976-08-26

1979-05-22

Hecker, Stuart N.

Static information storage and retrieval

Addressing

364200, 365238, G11C 800

Patent

active

041562909

ABSTRACT:
A memory addressing device for a memory divided in a plurality of elements each storing a plurality of information words. Each address for the memory comprises a first part which controls addressing means which address all the words of the memory elements stored in the address identified by said first part. All the addressed words are stored in corresponding output registers of the memory elements. The second part of the address enables the selection of the output register associated therewith. Consequently the reading operation for a block of information requires only one memory access time plus the read time of the output registers.

REFERENCES:
patent: 3618040 (1971-11-01), Iwamoto et al.
patent: 3618041 (1971-11-01), Horikoshi
patent: 3691538 (1972-09-01), Haney et al.
Beausoleil et al., "Hierarchical Storage Chip," vol. 16, No. 5 of IBM Tech. Disc. Bull., pp. 1364-1365, 10/1973.

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