High speed phase locked loop tuning system

Details High speed phase locked loop tuning system High speed phase locked loop tuning system

1977-12-06

1979-05-22

Griffin, Robert L.

325464, H04B 126

Patent

active

041561970

ABSTRACT:
An all-channel PLL tuning system includes LOF counters, a comparator producing an equality pulse each time the LOF count matches a preselected channel number count and a digital phase-frequency comparator comparing the equality pulses with reference pulses. High speed tuning is accomplished with the phase-frequency comparator arranged to yield immediate correct directional information. A reset pulse is generated for every other equality pulse and forces the equality and reference pulses to have the same initial phase and the digital phase-frequency comparator into one of its stable states corresponding to the desired output condition. The output directional information from the phase comparator is stored and tuning proceeds at high speed until a change in directional information occurs, indicating that the correct tuning frequency has been passed. Normal PLL operation then ensues.

REFERENCES:
patent: 3641434 (1972-02-01), Yates et al.
patent: 4031549 (1977-06-01), Rast et al.
patent: 4070629 (1978-01-01), Merrell

Affiliated with

Also associated with

Rating

High speed phase locked loop tuning system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed phase locked loop tuning system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed phase locked loop tuning system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1043034