Semiconductor memory with a clocked access code for test mode en

Details Semiconductor memory with a clocked access code for test mode en Semiconductor memory with a clocked access code for test mode en

1990-08-17

1991-12-10

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 36518903, 371 211, G11C 700

Patent

active

050721372

ABSTRACT:
An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that is is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgement of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

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McAdams et al., "A 1-Mbit CMOS Dynamic RAM with Design for Test Functions", IEEE Journal of Solid-State Circuits (Oct. 1986), vol. SC-21, No. 5, pp. 635-642.
Shimada et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits (Feb. 1988), vol. 23, No. 1, pp. 53-58.

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