Boots – shoes – and leggings
Patent
1976-05-27
1977-12-27
Thomas, James D.
Boots, shoes, and leggings
G06F 1516, G06F 1300
Patent
active
040658090
ABSTRACT:
A microcomputer system comprising two microcomputers, a read only memory (hereinafter abbreviated as "ROM") and a random access memory (hereinafter abbreviated as "RAM") exclusively used with each of the two microcomputers and a common RAM accessible from the two microcomputers, wherein the microcomputers and memories are connected together; there are provided between the microcomputers and common RAM an address decoder for detecting the access of the respective microcomputers to the common RAM and a control flip-flop circuit which is set when one of the two microcomputers completes a memory access cycle and is reset when the other finishes a memory access cycle; when the transfer of data is not carried out between the two microcomputers, then these microcomputers generally make an access to the corresponding exclusive memories; only when an access to the common RAM is made by the two microcomputers substantially at the same time, then the flip-flop circuit places one of the two microcomputers in a waiting position for memory access until the other finishes a memory access cycle; and in any other case, the two microcomputers carry out arithmetic operation independently of each other.
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IBM Technical Disclosure Bulletin, "Multiprocessing Storage Priority Network", Capowski, Jones, Meschi, vol. 14, No. 10, Mar. 1972, pp. 3141-3143.
"Multiprocessing Storage Conflict Resolution Technique", Duke, Messina, IBM Technical Disclosure Bulletin, vol. 15, No. 10, Mar. 1973, pp. 3232-3233.
Thomas James D.
Tokyo Shibaura Electric Co. Ltd.
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