Self-aligned double implanted short channel V-groove MOS device

Details Self-aligned double implanted short channel V-groove MOS device Self-aligned double implanted short channel V-groove MOS device

1976-10-18

1977-12-27

Miller, Jr., Stanley D.

357 23, 357 46, 357 55, H01L 2704, H01L 2978

Patent

active

040657833

ABSTRACT:
A short-channel V-groove MOS transistor is provided having laterally disposed source, drain, gate dielectric on the same face of a lightly p-doped substrate. Using ion implantation, a heavily doped vertical channel layer is symmetrically provided below and between the drain and the source in the substrate and being self-aligned to the gate which is formed in the V-groove by a silicon dioxide layer and a conductor layer. Appropriate leads contact the gate conductor, the drain and the source. Such transistor can be incorporated in an integrated circuit to form an inverter circuit with a lateral depletion-mode V-MOS as a load transistor.

REFERENCES:
patent: 3806371 (1974-04-01), Barone
patent: 4000429 (1976-12-01), Yoshida et al.
Holmes et al., "UMOS-A New Integrated Circuit Technology", Solid-State Electronics, Aug. 1974, vol. 17, pp. 791-797, Pergamon Press.
Stone et al., "Recent Advances in Ion Implantation-A State of the Art Review", Solid State Technology, June 1976, pp. 35-44.
Electronics, Apr. 1, 1976, pp. 76-81.

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