Vertical memory cell array and method of fabrication

Details Vertical memory cell array and method of fabrication Vertical memory cell array and method of fabrication

1990-06-28

1991-12-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 52, 437 59, 437203, 357 234, 357 235, H01L 21265

Patent

active

050717820

ABSTRACT:
A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked--a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

REFERENCES:
patent: 3975221 (1976-08-01), Rodgers
patent: 4169291 (1979-09-01), Rossler
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4975383 (1990-12-01), Baglee
patent: 4987090 (1991-01-01), Hsu

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