Split-polysilicon CMOS DRAM process incorporating self-aligned s

Details Split-polysilicon CMOS DRAM process incorporating self-aligned s Split-polysilicon CMOS DRAM process incorporating self-aligned s

1990-03-12

1991-06-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 52, 437 57, 437 34, 357 236, H01L 21265, H01L 21336, H01L 27092, H01L 27108

Patent

active

050266578

ABSTRACT:
A split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates and N+ regions with a minimum of additional processing steps. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the process avoids the problems that may be created by the double etching of the field oxide and active area regions that has heretofore been required for self-aligned silidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric. Although this process precludes the silicidation of the sources and drains of P-channel transistors, silicidation of other important regions is accomplished with very few steps required beyond those required for the basic split-polysilicon CMOS process without self-aligned silicidation of conductive regions.

REFERENCES:
patent: 4561170 (1985-12-01), Doering et al.
patent: 4871688 (1989-10-01), Lowrey
patent: 4945066 (1990-07-01), Kang et al.
patent: 4957878 (1990-09-01), Lowrey et al.

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