Process of fabricating a heterojunction field effect transistor

Details Process of fabricating a heterojunction field effect transistor Process of fabricating a heterojunction field effect transistor

1989-09-21

1991-06-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437107, 437126, 437132, 437912, 437105, 148DIG72, 148DIG169, 148DIG29, H01L 2120

Patent

active

050266551

ABSTRACT:
For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.

REFERENCES:
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patent: 4171234 (1979-10-01), Nagata et al.
patent: 4325747 (1982-04-01), Ristow
patent: 4550031 (1985-10-01), Abrokwah
patent: 4739385 (1988-04-01), Bethea et al.
patent: 4797374 (1989-01-01), Scott et al.
patent: 4839307 (1989-06-01), Imanaka et al.

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