Method and apparatus for testing and verifying the operability o

Details Method and apparatus for testing and verifying the operability o Method and apparatus for testing and verifying the operability o

1981-05-15

1984-02-21

Smith, Jerry

Excavating

371 16, G06F 1100

Patent

active

044334125

ABSTRACT:
When a state machine such as a computer is inoperative, the flow of data can occur in so many different ways that it is at times difficult to ascertain the portions of the state machine that are causing the problems. Whether the problems are caused by original design or later failure of components, the present invention can determine at least the general area of the problem and often the specific bit introducing the problem, by setting a predefined control bit pattern into a register and ascertaining whether or not the bit pattern returned to the register after a predefined sequence of operations matches design expectations. As illustrated, this may take the form of serially inserting data into a normally parallel operated register to form the predefined control bit pattern, which then is applied to a sequencer whose output address is used to address a word in ROM, and the addressed word as well as the address itself, is loaded into the register. The address and addressed word are then compared with design expectations to determine whether or not there is a problem with that particular instruction or that particular location in ROM.

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