Intersystem translation logic system

Details Intersystem translation logic system Intersystem translation logic system

1980-12-15

1984-02-21

Chan, Eddie P.

Boots, shoes, and leggings

G06F 304

Patent

active

044333765

ABSTRACT:
A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.

REFERENCES:
patent: 3648256 (1972-03-01), Paine et al.
patent: 3889237 (1975-06-01), Alferness et al.
patent: 3988716 (1976-10-01), Fletcher et al.
patent: 4007450 (1977-02-01), Haibt et al.
patent: 4035777 (1977-07-01), Moreton
patent: 4041472 (1977-08-01), Shah et al.
patent: 4047162 (1977-09-01), Dorey et al.
patent: 4096566 (1978-06-01), Borie et al.
patent: 4099233 (1978-07-01), Barbagelata et al.
patent: 4276594 (1981-06-01), Morley

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