Data receiver interface circuit

Multiplex communications – Wide area network – Packet switching

Patent

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Details

H04J 306

Patent

active

049742256

ABSTRACT:
A data receiver interface circuit is provided with a circuit for accepting correctly framed data. The plurality of data bits sandwiched between a pair of frame pulses is temporarily stored while the number of clock cycles occurring between the frame pulses is determined to be a valid number. The data is accepted by the receiver if the number of clock cycles occurring between the pair of successive frame pulses is a valid number.

REFERENCES:
patent: 3928727 (1975-12-01), Roche
patent: 4282600 (1981-08-01), Zemanek
patent: 4323790 (1982-04-01), Dunning et al.
patent: 4353129 (1982-10-01), Nishiwaki
patent: 4596026 (1986-06-01), Cease et al.

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