Generalized digital multiplier and digital filter using said mul

Details Generalized digital multiplier and digital filter using said mul Generalized digital multiplier and digital filter using said mul

1989-01-24

1990-11-27

Malzahn, David H.

Boots, shoes, and leggings

36472416, G06F 750

Patent

active

049741861

ABSTRACT:
The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.

REFERENCES:
patent: 4490805 (1984-12-01), Tamura
patent: 4573136 (1986-02-01), Rossiter
patent: 4616330 (1986-10-01), Betz

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