Clock pulse generating circuit

Details Clock pulse generating circuit Clock pulse generating circuit

1990-03-13

1990-11-27

Shepperd, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358149, 358158, H04N 504

Patent

active

049740814

ABSTRACT:
A clock pulse generating circuit is provided which is capable of generating a stabilized clock pulse without being effected by disturbance due to the vertical equalizer pulse. The clock pulse generating circuit includes a PLL circuit for generating a clock pulse which is phase-synchronized with an input signal. The circuit further includes a synchronizing circuit for generating a window pulse synchronized with the horizontal synchronizing signal by being operated with a clock pulse generated by the PLL circuit as a reference. The synchronization condition is judged with respect to the composite synchronizing signal and a gate circuit which permits passage of the composite synchronizing signal only during the period of existence of the window signal. Accordingly, the signal is constructed so as to select the composite synchronizing signal before passage through the gate in an asynchronous condition of the synchronizing circuit. Similarly, the composite synchronizing signal is passed after passage through the gate in a synchronous condition, the composite synchronizing signal being used as the input to the PLL circuit.

REFERENCES:
patent: 3904823 (1975-09-01), Van Straaten
patent: 4769704 (1988-09-01), Hirai et al.
patent: 4847678 (1989-07-01), McCauley

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