Microprocessor control system which selects operating instructio

Details Microprocessor control system which selects operating instructio Microprocessor control system which selects operating instructio

1994-07-11

1997-10-28

Harvey, Jack B.

395800, G06F 930

Patent

active

056825218

ABSTRACT:
A microprocessor which can simultaneously execute a plurality of instructions (predetermined number of instructions, i.e., m-instructions which are transferred to a plurality of registers. When the instructions within the m-instructions are transferred to the registers, the instructions are executed in order of the executable state of the instructions regardless of order of the transfer. Further, when n-instructions (n>m) are simultaneously set to the executable state for every one clock cycle, the n-instructions are executed in order of the transfer of the instructions. Accordingly, it is possible to realize high speed and effective execution of instructions.

REFERENCES:
patent: 4807115 (1989-02-01), Torng
patent: 5404470 (1995-04-01), Miyake
patent: 5497499 (1996-03-01), Garg et al.
Hennessy et al., "6.7 Advanced Pipelining--Dynamic Scheduling in Pipelines," Computer Architecture--A Quantitative Approach, 1990, pp. 290-305.
Johnson, Mike, "Chapter 7--Out-of-Order Issue," Superscalar Microprocessor Design, 1991, pp. 127-146.

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