Parallel computer system for performing barrier synchronization

Details Parallel computer system for performing barrier synchronization Parallel computer system for performing barrier synchronization

1995-08-14

1997-10-28

Lee, Thomas C.

Boots, shoes, and leggings

39520013, 395250, 395858, 395872, 3642841, G06F 1300

Patent

active

056824807

ABSTRACT:
In a network-connected multiprocessor computer system, good cost performance and multifunctional network control is realized. In a computer system in which a plurality of processors are connected through a network, an interrupting signal line is provided in additional transmission lines. A packet is used for inter-processor communication, and a barrier synchronization packet of a fixed length is used in barrier synchronization processing. Although a barrier synchronization packet is transferred from a sending control circuit through the same transmission line for an ordinary packet, an interrupting signal is also transferred through the interrupting signal line at the same time. On the other hand, a receiving control circuit is provided with a priority control circuit in which the highest priority is given to a barrier synchronization packet, so that in response to an interrupting signal on the interrupting signal line, a barrier synchronization packet is sent to a processor without being written in a register file provided for storing an ordinary packet.

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T. Hori, et al. "AP 1000 Architecture and Performance Analysis", CPSY 91-26, pp. 172-175.

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