Nonvolatile semiconductor memory device having suitable writing

Details Nonvolatile semiconductor memory device having suitable writing Nonvolatile semiconductor memory device having suitable writing

1996-03-29

1997-10-28

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 365236, G11C 1134

Patent

active

056823460

ABSTRACT:
According to the present invention, a voltage level for boosting a writing voltage to be supplied to memory cells of a memory cell array, and writing time are optimized in consideration of writing efficiency and a distribution of threshold voltage. A boosting circuit boosts the writing voltage to be supplied to memory cells. A counter counts the number of writing times in accordance with a signal of a timer. The timer outputs the signal used to count the number of writing times at a fixed interval from a first writing time until an arbitrary writing time in counting a predetermined number of writing times by the counter and to count the number of writing times at an interval when the number of writing times is gradually increased after the arbitrary writing time in order to control supplying time of the writing voltage to the memory cells. Additionally, a voltage control circuit gradually divides a boost level due to the boosting circuit in accordance with the arbitrary number of writing times until the writing voltage reaches a predetermined upper limit, and maintains the writing voltage when the writing voltage reaches the predetermined upper limit.

REFERENCES:
patent: 5053990 (1991-10-01), Kreifels
patent: 5379256 (1995-01-01), Tanaka
patent: 5544118 (1996-08-01), Harari
patent: 5555204 (1996-09-01), Endoh
Tomoharu Tanaka, et al., "A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution", ULSI Research Center, Toshiba Corporation, 1990 Symposium on VISI Circuits, pp. 105-106.

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