Signal processor for digital echo canceller

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1791702, H04B 320, G06F 752

Patent

active

042837707

ABSTRACT:
A processor for an echo canceller generates an estimate of an actual echo on an echo path and applies the same to a subtractor circuit in the path to cancel the echo. To generate the echo estimate, the processor multiplies A-law digitally encoded samples of signals which cause the echo by A-law digitally encoded samples of impulse responses of the echo path and sums a plurality of the products. The particular manner of multiplying the A-law samples produces a product which is a precise linear representation of the product of the linear equivalents of the samples, and no errors or approximations occur in the multiplication or in generation of the echo estimate.

REFERENCES:
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patent: 4007341 (1977-02-01), Sourgens et al.
patent: 4064379 (1977-12-01), Horna
patent: 4113997 (1978-09-01), Horna
patent: 4144417 (1979-03-01), Oshima et al.
patent: 4163287 (1979-07-01), Munter et al.

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