Method and apparatus for reducing phase lag resulting from digit

Details Method and apparatus for reducing phase lag resulting from digit Method and apparatus for reducing phase lag resulting from digit

1996-02-21

1997-10-28

Hoff, Marc S.

Coded data generation or conversion

Converter compensation

360 7705, H03M 106, G11B 5576

Patent

active

056821590

ABSTRACT:
A method and apparatus for implementing a zero order hold function in the digital to analog conversion process in a digital control system reduces the phase lag contributed by the digital to analog conversion process relative to a conventional implementation of the zero order hold function. The apparatus for implementing the reduced phase lag zero order hold function employs a digital signal processor, a plurality of digital buffers, a digital multiplexing element, and a digital to analog converter. Phase lag is reduced by generating, from the digital to analog converter, for a fraction of the sample period, a waveform having a constant analog voltage with an amplitude which is scaled by the reciprocal of said fraction relative to a conventional zero order hold function. During the remainder of the sample period a substantially constant offset analog voltage is generated by the digital to analog converter. Alternatively, the time compression and amplitude scaling required to implement the reduced phase lag zero order hold function can be performed within the digital signal processor in the digital control system.

REFERENCES:
patent: 4315199 (1982-02-01), Kyomasu et al.
patent: 5105318 (1992-04-01), Tsuneta et al.
patent: 5153787 (1992-10-01), Sidman
patent: 5202821 (1993-04-01), Bauck et al.
patent: 5220468 (1993-06-01), Sidman
patent: 5533072 (1996-07-01), Georgiou et al.

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