Control circuit for floating gate four-quadrant analog multiplie

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307201, 364807, H03K 522, H03K 1908

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active

050216937

ABSTRACT:
Disclosed is an electronic circuit comprising commonly connecting the gate end of a first transistor having a floating gate and the source end and the drain end of a second transistor having a floating gate to a first control input terminal, and commonly connecting the source end and the drain end of the first transistor and the normal gate end of the second transistor to a second control input terminal. The electronic circuit can repeatedly set and maintain accumulation charge amounts of the respective floating gates of the first and the second transistor at predetermined values. Also disclosed is an electronic circuit including the above electronic circuit, and further comprising commonly connecting the respective souce ends of a third and a fourth transistor to a first terminal to compose a first differential couple, providing a current source between the first terminal and a power source end or and earthed end, connecting the floating gates of the first and the third transistor together, connecting the floating gates of the second and the fourth transistor together, connecting the normal gate end of the third transistor to a first positive input terminal, and connecting the normal gate end of the fourth transistor to a first negative input terminal. The so-composed electronic circuit can repeatedly set and maintain threshold values in differential amplification at respective predetermined values. Further disclosed is an analog multiplication circuit comprising combination of these electronic circuits and an amplification circuit, which can repeatedly set and maintain weight concerning multiplication factors at predetermined values.

REFERENCES:
patent: 4663740 (1987-05-01), Ebel
patent: 4950917 (1990-08-01), Holler et al.
patent: 4956564 (1990-09-01), Holler et al.
patent: 4961002 (1990-10-01), Tam et al.
U. Rueckert et al., "VLSI Architectures for Associative Networks", International Symposium on Circuits and Systems Proceedings, vol. 1, Jun. 7-9, 1988, pp. 755-758, IEEE.
Mark Holler et al., "An Electrically Trainable Artificial Neural Network (ETANN) with 10240 `Floating Gate` Synapses", IJCNN International Joint Conference on Neural Networks, 1989, pp. II-191-II-196.

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