Programmable logic array apparatus

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307468, 307469, 307481, 364716, H03K 1704

Patent

active

050216902

ABSTRACT:
An apparatus adaptable for use as a programmable logic array as disclosed for receiving control signals from a signal source and producing resultant output signals logically related to the control signals according to a program which is comprised of a plurality of program instructions, each of which is identified by an address. The apparatus includes a clock for generating a plurality of clock signals and first and second iteration processing circuits for effecting iteration operations upon the input signals and producing resultant output signals on a plurality of output lines. The apparatus further includes a plurality of minterm lines common to the first and second iteration processing circuits. The first iteration processing circuit includes a plurality of first switching devices connected in series within selected of the minterm lines and gated by the input signals. The program is executed within the first iteration processing circuit by selectively gating appropriate of the switching devices to define a continuous path for discharging selected of the minterm lines. Placement of the first switching devices within the first iteration processing circuit is defined by the program. Selection of the minterm lines for participation in a respective program instruction is determined according to the address of the particular program instruction, which address is stored in a cyclic memory device. The apparatus is arranged in a plurality of blocks, each of which blocks implements a predetermined group of program instructions in a pipeline manner.

REFERENCES:
patent: 4534008 (1985-08-01), Fuchs et al.
patent: 4725748 (1988-02-01), Kondo et al.
patent: 4769562 (1988-09-01), Ghisio
patent: 4902918 (1990-02-01), Sugeno et al.

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