Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1983-09-23

1985-12-31

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365189, G11C 700

Patent

active

045625557

ABSTRACT:
An address multiplex type system for a dynamic RAM includes a memory cell array having a plurality of memory cells which are simultaneously selected by signals output from an address decoder, a decoder, and a shift register. The dynamic RAM further includes a selecting circuit which receives a plurality of address signals applied externally through one of a plurality of pins of a package in a time-sharing manner and makes it possible to write or read data into or from one memory cell of the plurality of memory cells selected. The dynamic RAM can read out or write in serially data of a plurality of memory cells selected from the memory cell array when a shift register operates. The dynamic RAM can also read or write data serially into or from a plurality of memory cells selected from the memory cell array simply by connecting the pin to a predetermined potential. When the data is written or read serially, the pin arrangement of the package of a 256K bit dynamic RAM can be substantially the same as that of the package of a 64K bit dynamic RAM. Hence, compatibility can be established between the 256K bit dynamic RAM and a 64K bit dynamic RAM.

REFERENCES:
patent: 4402067 (1983-08-01), Moss et al.
Charles Cohen, "NEC Slates Moly for 256-K Ram", Electronics, Sep. 22, 1981, pp. 78-79.
Douglas Eidsmore, "256K DRAM Highly Immune to Soft Errors", Computer Design, vol. 4, Apr. 1982, pp. 42 and 46.

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