Dynamic row buffer circuit for DRAM

Details Dynamic row buffer circuit for DRAM Dynamic row buffer circuit for DRAM

1984-06-01

1987-03-10

Hoffman, James R.

Boots, shoes, and leggings

G06F 1200, G06F 1338

Patent

active

046495169

ABSTRACT:
A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4356411 (1982-10-01), Suzuki et al.
patent: 4359647 (1982-11-01), Trinkl
patent: 4386282 (1983-05-01), Scavuzzo
patent: 4422160 (1983-12-01), Watanabe

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