Multiple port memory with port decode error detector

Details Multiple port memory with port decode error detector Multiple port memory with port decode error detector

1984-04-02

1987-03-10

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 51, G06F 1300, G06F 1100

Patent

active

046494758

ABSTRACT:
An improved multiple port memory system has a priority network for selecting between multiple units seeking access thereto. The priority network responds to requests for access and provides encoded port identifying signals indicative of the port to have access. Decode circuitry decodes the encoded port identifying signals and provides unique port enabling signals for the selected port. Decode error detection circuitry responds to the decoded port enabling signals and provides a decode error indication any time multiple port enabling signals are detected as occurring simultaneously. Port Code error detecting circuitry respond to the encoded port identifying signals and the decoded port enabling signals to provide a code error indicating signal when a port code error condition is detected.

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