Fault diagnosis apparatus and method for sequence control system

Registers – Systems controlled by data bearing records – Time analysis

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G06F 1100

Patent

active

041834623

ABSTRACT:
A method and an apparatus for diagnosing a fault in a sequence control system performing control in accordance with a predetermined sequence, wherein memory means having bits corresponding to respective ones of a plurality of predetermined sequence steps is provided. The sequence of steps actually applied to an object to be controlled are sequentially stored in corresponding bits. Each time a sequence step is applied to the object to be controlled, the contents of the memory means are checked to see whether or not any of the sequence steps applied thus far have been skipped. If any sequence step has been skipped, a fault is determined. Preferably, a fault is also determined when any of the intervals of sequence steps successively applied exceeds a predetermined length of time. Upon determination of a fault, the sequence step associated with the fault is identified, and the control circuit associated with the sequence step in fault is preferably displayed.

REFERENCES:
patent: 3225205 (1965-12-01), Berkin
patent: 3320440 (1967-05-01), Reed
patent: 3713095 (1973-01-01), McPherson
patent: 3899665 (1975-08-01), Gaon
patent: 3939453 (1976-02-01), Schroeder
patent: 4023109 (1977-05-01), Shreve

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