Video signal delay circuit

Details Video signal delay circuit Video signal delay circuit

1985-03-05

1987-03-10

Masinick, Michael A.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358167, 358213, H04N 514, H04N 5213, H04N 314

Patent

active

046494278

ABSTRACT:
A video signal delay circuit comprises a plurality of rows of input horizontal transfer registers, a plurality of input vertical transfer gates, a plurality of columns of vertical transfer registers, a plurality of output vertical transfer gates, a plurality of rows of output horizontal transfer registers, a horizontal transfer clock pulse generating circuit, a vertical transfer clock pulse generating circuit, and a selecting circuit. The selecting circuit selectively supplies a horizontal transfer clock pulse to an arbitrarily selected one of the plurality of rows of input horizontal transfer registers and to an arbitrarily selected one of the plurality of rows of output horizontal transfer registers based on at least horizontal and vertical synchronizing signals within an input composite video signal. The selecting circuit supplies the input composite video signal to the arbitrarily selected one of the plurality of rows of input horizontal transfer registers and selectively obtains an output composite video signal of only the arbitrarily selected one of the plurality of rows of output horizontal transfer registers.

REFERENCES:
patent: 4349743 (1982-09-01), Ohba et al.
patent: 4536795 (1985-08-01), Hirota et al.

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