Patent
1984-12-17
1987-03-10
Edlow, Martin H.
357 49, 357 16, 357 50, 357 56, 357 89, 357 46, 357 48, 357 54, H01L 2972
Patent
active
046494111
ABSTRACT:
A gallium arsenide integrated circuit structure is disclosed wherein each transistor has only two of three terminals exposed at the semiconductor surface, thereby decreasing both the area of the structure and parasitic wiring capacitance. A dielectric buried layer overlies a portion of the substrate and isolates a first region from the remaining chip. This first region serves as common terminals of two or more transistors. Aluminum gallium arsenide is formed both above and below the base region for increasing the efficiency of the junction by eliminating the need for a heavily doped emitters, thereby allowing for symmetry of emitter and collector regions both on the semiconductor surface and below.
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Edlow Martin H.
Koch William E.
Mintel William A.
Motorola Inc.
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