Patent
1984-06-12
1987-03-10
Edlow, Martin H.
357 2311, 357 51, 357 54, H02L 2978
Patent
active
046494065
ABSTRACT:
In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell includes a base electrode, an insulating layer, and a counter electrode. The base electrode of each memory cell is partly superposed without contact on the base electrodes of other adjacent memory cells.
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Nakano Tomio
Sato Kimiaki
Takemae Yoshihiro
Crane Sara W.
Edlow Martin H.
Fujitsu Limited
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