Patent
1996-09-20
1998-09-15
Shah, Alpesh M.
395580, G06F 900
Patent
active
058093265
ABSTRACT:
A signal processor includes an instruction buffer for sequentially storing information on instructions output from an instruction cache, and a first register that detects that an instruction enters in an instruction loop. When the instruction loop is formed, a control circuit controls the instruction buffer to supply the instruction in the instruction loop from its storage while placing the instruction cache in an inactive state.
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Kabushiki Kaisha Toshiba
Shah Alpesh M.
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