Multiple instruction dispatch system for pipelined microprocesso

Details Multiple instruction dispatch system for pipelined microprocesso Multiple instruction dispatch system for pipelined microprocesso

1995-12-07

1998-09-15

Donaghue, Larry D.

395394, 395586, G06F 930

Patent

active

058093249

ABSTRACT:
A microprocessor with a dispatch unit which dispatches a maximum number of instructions each cycle, without splitting into separate blocks after a branch instruction. A mispredicted branch is handled by setting a valid bit to invalid for instructions following the branch instruction in an outstanding instruction FIFO.

REFERENCES:
patent: 5542109 (1996-07-01), Blomgren et al.
patent: 5598546 (1997-01-01), Blomgren

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