Structure for physical fault simulation of digital logic

Details Structure for physical fault simulation of digital logic Structure for physical fault simulation of digital logic

1979-05-29

1981-12-29

Malzahn, David H.

Excavating

G06F 1122

Patent

active

043086160

ABSTRACT:
A shift register connected to elementary gates is added to a digital network to form a fault simulator. The shift register and the additional gates can select a connection from the digital network and simulate a fault on the selected connection. Connection selection is done at a speed comparable to that at which the digital network operates and fault simulation is nondestructive. By resetting the shift register the fault simulator performs as if the digital network were fault-free. To simulate certain faults in the digital network a predetermined fault injection pattern for the faults to be simulated is entered into the shift register.

REFERENCES:
patent: 3790885 (1974-02-01), James
patent: 3815025 (1974-06-01), Jordan
patent: 4204633 (1980-05-01), Goel
Maiden et al., "Error Injector Probe", IBM Tech. Disclosure Bulletin, vol. 18, No. 1, Jun., 1975, pp. 7-8.
Barnshaw, "Electronic Fault Injection Device", IBM Tech. Disclosure Bulletin, vol. 16, No. 10, Mar., 1974, pp. 3176-3178.
Tsiang et al., "Automatic Trouble Diagnosis of Complex Logic Circuits", The Bell System Technical Journal, vol. 18, No. 10, Mar. 1974, pp. 1177-1200.

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