Digital signal processing circuit

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Details

364754, 364724, G06F 738, G06F 744

Patent

active

046113053

ABSTRACT:
A digital signal processing circuit formed on a single integrated chip includes a multiplier for multiplying a multiplicand and multiplier signal to produce a multiple bit product signal having higher order bits delayed more than lower order bits; a first delay circuit for concatenating and delaying the multiplier and multiplicand signals to produce a delayed concatenated signal having higher order bits delayed more than lower order bits; a first selector for selectively supplying either the product signal, the delayed concatenated signal, or a concatenated signal formed from the multiplier and multiplicand signals, as a first selected signal; an adder for adding an input signal to the first selected signal to produce a summed signal; a second delay circuit for delaying a summed signal by a predetermined amount to produce a first delayed summand signal; a third delay circuit for delaying the summand signal to produce a second delayed summand signal having higher order bits delayed more than lower order bits; a second selector for selectively supplying either the first or second delayed summand signal to the adder as the input signal; a fourth delay circuit for delaying the summed signal by a predetermined amount to produce a first delayed summed signal; a fifth delay circuit for delaying the summed signal to produce a second delayed summed signal having lower order bits delayed more than higher order bits; and a third selector for selectively supplying either the first or second delayed summed signal as an output of the processing circuit.

REFERENCES:
patent: 3805037 (1974-04-01), Ellison
patent: 4344148 (1982-08-01), Brantingham et al.
patent: 4407018 (1983-09-01), Kanemasa
patent: 4443859 (1984-04-01), Wiggins
patent: 4449194 (1984-05-01), Wilhelm
patent: 4513388 (1985-04-01), Veendrick et al.

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