Method of fabricating electrically erasable read only memory cel

Details Method of fabricating electrically erasable read only memory cel Method of fabricating electrically erasable read only memory cel

1991-05-17

1993-01-19

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 48, 437203, H01L 2170

Patent

active

051806800

ABSTRACT:
An EPROM cell on a semiconductor substrate having a trench containing a source region in the bottom thereof, insulated floating gates on opposite sidewalls of the trench, and a control gate overlying the floating gates. Drain regions are provided beneath the top surface of the substrate, adjacent to the floating gates, which are electrically connected by a conductive stripe on the surface of the substrate that extends transverse to the trench axis.
A method of fabricating an EPROM cell by forming a trench in a semiconductor substrate. An insulated floating gate of polycrystalline silicon is formed on the sidewalls of the trench. Doped regions are formed on the surface of the substrate and in the trench bottom. A control gate is formed over the floating gate. Electrical contact is established to the doped regions and the control gate.

REFERENCES:
patent: 4975384 (1990-12-01), Baglee
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5049515 (1991-09-01), Tzeng

Affiliated with

Also associated with

Rating

Method of fabricating electrically erasable read only memory cel does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating electrically erasable read only memory cel, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating electrically erasable read only memory cel will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-101853