1984-07-06
1986-09-09
James, Andrew J.
357 41, 357 42, H01L 2710, H01L 2702
Patent
active
046112367
ABSTRACT:
A masterslice semiconductor device has two kinds of basic cells including a first one having the same size same as that of ordinary basic cells in a prior art masterslice semiconductor device and a second one having a size larger than that of the first basic cell. A number of the large-sized basic cells are arranged along columns of a semiconductor substrate and constitute a plurality of basic cell arrays which are disposed along rows of the semiconductor substrate. Each of the basic cell arrays of the second basic cells is situated between two adjacent basic cell arrays of the first basic cells. Each of the regions occupied by the basic arrays of the second basic cells can be used for distributing interconnecting lines as in the prior art masterslice semiconductor device. At least one of the second basic cells in each of the regions serves to interconnect the first basic cells in adjacent basic cell arrays, and also provides an elementary circuit block, that is a unit cell, in conjunction with the first basic cells.
REFERENCES:
patent: 4006492 (1977-02-01), Eichelberger et al.
patent: 4161662 (1979-07-01), Malcolm et al.
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4412237 (1983-10-01), Matsumura et al.
Japanese Journal of Applied Physics, vol. 19, suppl. 19-1, 1980 pp. 203-206, Tokyo, JP, M. Ashida et al., "A 3000-Gate CMOS Masterslice LSI"; FIGS. 2-4; pp. 204, 205, paragraph 3: Structure of the LSI.
Fujitsu Limited
Jackson, Jr. Jerome
James Andrew J.
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