Method of making a flexible tester surface for testing integrate

Details Method of making a flexible tester surface for testing integrate Method of making a flexible tester surface for testing integrate

1989-11-14

1991-06-04

Hall, Carl E.

Metal working

Method of mechanical manufacture

Electrical device making

29407, 29832, 204 15, 324158P, 430316, 430318, 437 8, H05K 302

Patent

active

050202197

ABSTRACT:
Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD means. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.
The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.

REFERENCES:
patent: 3405361 (1968-10-01), Kattner et al.
patent: 3618201 (1971-11-01), Makimoto et al.
patent: 3702025 (1972-11-01), Archer
patent: 3835530 (1974-09-01), Kilby
patent: 4038599 (1977-07-01), Bove et al.
patent: 4065717 (1977-12-01), Kattner et al.
patent: 4566184 (1986-01-01), Higgins et al.
patent: 4573008 (1986-02-01), Lischke
patent: 4574235 (1986-03-01), Kelly et al.
patent: 4585727 (1986-04-01), Reams
patent: 4585991 (1986-04-01), Reid et al.
patent: 4590422 (1986-05-01), Milligan
patent: 4617730 (1986-10-01), Geldermans et al.
patent: 4636722 (1987-01-01), Andezzone
patent: 4644264 (1987-02-01), Beha et al.
patent: 4647851 (1987-03-01), Dugan
patent: 4649338 (1987-03-01), Dugan
patent: 4649339 (1987-03-01), Grangroth et al.
patent: 4686112 (1987-08-01), Hoffman
patent: 4697143 (1987-09-01), Lockwood et al.
patent: 4707657 (1987-11-01), Boegh-Petersen
patent: 4715928 (1987-12-01), Hamby
patent: 4755747 (1988-07-01), Sato
patent: 4799009 (1989-01-01), Tada et al.
patent: 4814283 (1989-03-01), Temple et al.
patent: 4820976 (1989-04-01), Brown
patent: 4853627 (1989-08-01), Gleason et al.
Wafer Scale Integration-Historical Perspective, N. R. Strader et al. (date unknown).
"Plastics That Conduct Electricity", R. B. Kaner and A. G. MacDiarmid, Scientific American, pp. 106-111, Feb. 1988.

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