Method of manufacturing semiconductor device utilizing multilaye

Details Method of manufacturing semiconductor device utilizing multilaye Method of manufacturing semiconductor device utilizing multilaye

1983-07-26

1985-12-31

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29579, 29591, H01L 21441

Patent

active

045611696

ABSTRACT:
In manufacturing a field effect transistor, a pattern which has a wider upper layer and a narrower lower layer is formed at a gate electrode position. Using the pattern as a mask, first and second impurity regions are formed on both the sides of a gate region by ion implantation. Subsequently, at least the lower layer is buried in a material, such as an organic high polymer material, having a selectivity in etching characteristics with respect to the pattern material. After removing the lower layer, an electrode material is embedded in the resulting hole so as to form a gate electrode.

REFERENCES:
patent: 3994758 (1976-11-01), Ogawa et al.
patent: 4182023 (1980-01-01), Cohen et al.
patent: 4213840 (1980-07-01), Omori et al.

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