Processing cell for fault tolerant arrays

Details Processing cell for fault tolerant arrays Processing cell for fault tolerant arrays

1991-02-22

1991-11-12

Chan, Eddie P.

Excavating

371 91, 371 113, 3642665, 3642677, 364268, 3642689, 3642683, 364DIG1, G06F 1116, G06F 1120

Patent

active

050653083

ABSTRACT:
A process cell is provided for use in constructing fault tolerant arrays. It contains a processor arranged to indicate a faulty or fault-free operational state. The cell is arranged to receive input from any one of the three western neighbors, and to provide output to any one of three eastern neighbors. It both generates and receives connection request and availability signals. Internal logic ensures its becoming connected as part of an operational (not necessarily straight) row of cells in an array if and only if the processor is fault-free and it receives at least one pair of true request and availability signals from respective eastern and western neighbors. The internal cell logic implements a priority scheme in which connection to a more northern neighbor to east or west is preferred to connection to one more southern. This avoids any mid-array connection hiatus. Further embodiments of the invention provide for configurable columns of cells in addition to the foregoing row reconfiguration.

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