Multiple register bank system for concurrent I/O operation in a

Details Multiple register bank system for concurrent I/O operation in a Multiple register bank system for concurrent I/O operation in a

1995-08-16

1997-10-21

Lee, Thomas C.

395856, 395858, G06F 1200

Patent

active

056806418

ABSTRACT:
A system and method is provided for use in register-based CPUs for processing data in the CPU register bank while concurrently loading and unloading data into additional register banks. The additional register banks are then sequentially connected to the CPU datapath for data processing. Interconnections between the various register banks in the CPU and appropriate data buses for performing the load/process/unload functions are controlled by a load/store control logic block which can be a simple state machine processor. The load/store control logic is triggered by a software instruction encountered at the end of particular computational routines during normal program execution. This software instruction replaces the need for separate load and store instructions and their attendant clock cycles. The invention substantially decreases unused data processor time since the arithmetic and logic unit (ALU) can be sequentially connected to register banks which have been pre-loaded with data for processing. The need to stop data processing through the ALU while data is loaded into an unloaded from the CPU register bank is eliminated. A method of register-based CPU concurrent I/O operation is also disclosed.

REFERENCES:
patent: 5163132 (1992-11-01), DuLac et al.
patent: 5185876 (1993-02-01), Nguyen et al.
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5313648 (1994-05-01), Ehlig et al.
R. Bhatia, M. Furuta and J. Ponce, Proceedings of the ICASSP -- 1991 International Conference on Acoustics, Speech, and Signal Processing, IEEE, Toronto, Canada, May 14-17, 1991, pp. 1085-1088.
S. Furber, VLSI RISC Architecture and Organization, Marcel Dekker, Inc., 1989, pp. 111-117, 123-131.
D. A. Patterson and John L. Hennessy, Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990, pp. 450-454.
R. Zaks, Programming the Z80, 3d Edition, SYBEX, Inc., 1982, pp. 61-65.
M. Slater, Microprocessor-Based Design, A Comprehensive Guide to Hardware Design, Prentice Hall, Inc., 1989, pp. 50-52.
i960.TM. CA Microprocessor User's Manual, Intel Corporation, 1992, pp. iii, 2-1 through 2-4, 3-30 through 3-33, 3-82, and 3-86 through 3-87.
M. Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991, pp. 41-45, 50-55, 159-163.
A. van Sommeren and C. Atack, The ARM RISC Chip, A Programmer's Guide, Addison-Wesley Publishing Co., 1993, pp. 21-35, 107-119.

Affiliated with

Also associated with

Rating

Multiple register bank system for concurrent I/O operation in a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple register bank system for concurrent I/O operation in a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple register bank system for concurrent I/O operation in a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1016045