Data processor with on-chip cache memory and purge controller re

Details Data processor with on-chip cache memory and purge controller re Data processor with on-chip cache memory and purge controller re

1992-11-18

1997-10-21

Pan, Daniel H.

Boots, shoes, and leggings

395462, 395467, 395450, 364DIG1, 364DIG2, G06F 9312, G06F 930

Patent

active

056806310

ABSTRACT:
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

REFERENCES:
patent: 3618041 (1971-11-01), Horikoshi
patent: 3781823 (1973-12-01), Senese
patent: 3845474 (1974-10-01), Lange et al.
patent: 3859636 (1975-01-01), Cook
patent: 3979726 (1976-09-01), Lange et al.
patent: 4011547 (1977-03-01), Kimmel
patent: 4179736 (1979-12-01), Wilhite et al.
patent: 4312034 (1982-01-01), Gunter et al.
patent: 4325121 (1982-04-01), Gunter et al.
patent: 4342078 (1982-07-01), Tredennick et al.
patent: 4456954 (1984-06-01), Bullions, III et al.
patent: 4471429 (1984-09-01), Porter et al.
patent: 4471432 (1984-09-01), Wilhite et al.
patent: 4502110 (1985-02-01), Saito
patent: 4511960 (1985-04-01), Boudreau
patent: 4521850 (1985-06-01), Wilhite et al.
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4530050 (1985-07-01), Fukunaga et al.
patent: 4602368 (1986-07-01), Circello et al.
patent: 4608633 (1986-08-01), Boothroyd et al.
patent: 4675806 (1987-06-01), Uchida
patent: 4713752 (1987-12-01), Tone
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4740889 (1988-04-01), Motersole et al.
patent: 4775955 (1988-10-01), Liu
"Integrated MMU, cache raise system-level issues", Sorin la cobovici et al., Computer Design, vol. 26, No.10, May 15, 1987, pp. 75-79.
MC68020 32-Bit Microprocessor User's Manual, Second Edition, Englewood Cliffs, N.J., Prentice Hall, Inc., 1984. pp. 1-2, 1-9/1-10, 6-8, 6-9, 7-1 to 7-4.

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