Clock synchronization device in data transmission system

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

328 63, 370108, 375110, H04L 700

Patent

active

045731730

ABSTRACT:
A circuit for obtaining a clock pulse synchronized to a data signal received at a receiving side, which has a plurality of clock pulses having a repetition frequency equal to that of a clock in a transmission side but being different from one another in phase. On reception of the first data bit of the received data signal, the timing of the first data bit is detected at a detection circuit in reference to the plurality of clock pulses. According to the detected timing, a selector circuit selects one of the plurality of clock pulses with a predetermined constant phase difference from the received data signal.
The detection circuit comprises D-type flip-flops, and the selector circuit comprises AND gates.

REFERENCES:
patent: 4119796 (1978-10-01), Jones
patent: 4208724 (1980-06-01), Rattlingourd
patent: 4400666 (1983-08-01), Sekiguchi

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