Semiconductor logic circuit with noise suppression circuit

Details Semiconductor logic circuit with noise suppression circuit Semiconductor logic circuit with noise suppression circuit

1989-08-23

1991-11-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307451, 307481, 307542, 307546, 307570, 307572, H03K 1912, H03K 19092

Patent

active

050650483

ABSTRACT:
A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

REFERENCES:
patent: 4710650 (1987-12-01), Shoji
patent: 4797580 (1989-01-01), Sunter
patent: 4804868 (1989-02-01), Masuda et al.
patent: 4837463 (1989-06-01), Okitaka et al.
1987 "High Speed Circuit Technology for Mainframe VLSI" Symposium on VLSI Circuit Uchida, et al. pp. 93-94.
Session IV: High-Speed Circuit Technology WAM 4,6: "Two CMOS 0.5 m 32b Digital Macros" by Chih-Liang Cren et al. pp. 62-63.
1977 IEEE Solid State Circuit Conference "A CMOS Microprocessor for Telecommunication Applications" Cooper et al. pp. 138-139.

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