Method of controlling channel length by implanting through polyc

Details Method of controlling channel length by implanting through polyc Method of controlling channel length by implanting through polyc

1981-09-23

1983-12-20

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 148 15, 148187, 357 91, B01J 1700, H01L 21265

Patent

active

044208707

ABSTRACT:
A method for manufacturing semiconductor devices containing at least one MOS field effect transistor (FET) so as to control the effective channel length thereof and prevent channel-shortening. A mask wider than the desired MOS FET channel is formed on the surface of a first single-crystalline silicon semiconductor region, and the lattice structure of the unmasked surface portions thereof are randomized or disordered by silicon ion-implantation or by etching. After removal of the mask, epitaxial growth produces a polycrystalline region on the randomized regions and a second single-crystalline region on the previously masked region. An insulated gate electrode narrower than the single-crystalline region is formed centrally thereupon for serving as a mask during impurity implantation into the polycrystalline region and the portions of the second single-crystalline region adjacent thereto. In subsequent heat treatment impurity diffusion is slower in the second single-crystalline region that in the polycrystalline region, advantageously inhibiting lateral impurity diffusion from the second single-crystalline region into the channel underlying the gate electrode, thereby to control channel shortening, while at the same time permitting deep impurity diffusion in the polycrystalline regions for reducing resistance of the diffusion layer as a whole.

REFERENCES:
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patent: 4167806 (1979-09-01), Kumurdjian
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Lau, S. S., J. Vac. Sci. Technol. 15(5) (1978) 1656.
Thompson et al., Radiation Effects, 52 (1980) 69-84.
Tsai et al., J. Appl. Phy. 50 (1979) 183.

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