Single-FIFO high speed combining switch

Details Single-FIFO high speed combining switch Single-FIFO high speed combining switch

1989-01-27

1991-09-03

Fleming, Michael R.

Boots, shoes, and leggings

3642443, 3642397, 3642841, 3642843, G06F 1300, G06F 700

Patent

active

050460005

ABSTRACT:
A combining switch 10 includes a two input multiplexer 12 which receives I and J inputs from data processors and directs one of the incoming messages, if there are no contentions of congestions at a switch output port 14 and a Quene FIFO 16 is empty, directly to the output port 14 for transmission to one of a plurality of memory modules. If the output port 14 is busy and the Queue 16 is empty the incoming message is routed to the Queue FIFO 16 for storage. If the Queue FIFO 16 is not empty the incoming message is first compared by a comparator 20 to all existing messages stored in the Queue FIFO 16 to determine if the incoming messasge is destined for a memory address which already has a queued message. If no match is determined by comparator 20 the incoming message is routed to the Queue FIFO 16 for storage. If comparator 20 determines that the memory address and operation type of the incoming message matches that of a message already stored in the Queue FIFO 16 both the incoming message and the queued message are applied to a message combining ALU 26. The ALU 26 generates a combined message which is stored at the same Queue 16 location as the queued message which generated a comparison match with the incoming message.

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"Design of a Combining Network for the RP3 Project", by Yarsun Hsu et al., International Symposium VSLI Technology Systems and Applications, 1987 pp. 349-353.
"High Performance Microprocessor Memory System", by S. J. Ramer et al., IBM Technical Disclosure Bulletin, vol. 21, No. 3, Aug. 1988.

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