Data processor

Details Data processor Data processor

1988-10-28

1991-09-03

Fleming, Michael R.

Boots, shoes, and leggings

364239, 3642426, 36424291, G06F 1314

Patent

active

050459970

ABSTRACT:
The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver memory. When the high-speed memory is filled with data, the data is processed by the CPU, and the packet is transmitted from the high-speed memory via the transmitter memory. A competition control section is provided to control data accesses in the sequential operation.

REFERENCES:
patent: 4245299 (1981-01-01), Woods et al.
patent: 4453214 (1984-06-01), Adcock
patent: 4536839 (1985-08-01), Shah et al.
patent: 4639862 (1987-01-01), Wada et al.
patent: 4654788 (1987-03-01), Boudreau et al.
patent: 4780812 (1988-10-01), Freestone et al.
Intel Advance Information, "iMCC Map Communications Controller Component Set", Oct. 1987.

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