Multiprocessor cache memory housekeeping

Details Multiprocessor cache memory housekeeping Multiprocessor cache memory housekeeping

1989-11-15

1991-09-03

Chan, Eddie P.

Boots, shoes, and leggings

364243, 3642434, 36424341, 36424344, G06F 1208, G06F 1212

Patent

active

050459961

ABSTRACT:
Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a launder is followed by a flag reset invalidating the entries in the address set. Also, the command indicates which of the valid flags should be reset. In demapping, only the flags making an entry inaccessible to the cache's processor are reset. The entries in the address set are selected based on two numbers which together provide a base three number. Each base three digit of this number specifies whether the corresponding real address bit of the entry will match if it is one or zero or "don't care". This permits housekeeping on any consecutive range of N addresses by specifying no more than 2 log.sub.2 N address sets which exactly cover that range. A processor initiates housekeeping by causing its cache to send a command indicating the operations to be performed and the numbers selecting the address set. In response, all caches pull down a line indicating housekeeping in progress, and that line remains down until the last cache has completed housekeeping, at which time the initiating processor is freed. Meanwhile, however, each of the caches interrupts housekeeping if it receives a command, so that non-housekeeping functions are not delayed by housekeeping. For this purpose, the execution of a housekeeping command is divided into incremental write back and flag reset operations after each of which the cache tests whether it has received a command. If not, housekeeping continues with the next write back or flag reset operation.

REFERENCES:
patent: 4264953 (1981-04-01), Douglas et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4504902 (1985-03-01), Gallaher et al.
patent: 4506323 (1985-03-01), Pusic et al.
patent: 4523206 (1985-06-01), Sassier
patent: 4530055 (1985-07-01), Hamstra et al.
patent: 4577274 (1986-03-01), Ho et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4638431 (1987-01-01), Nishimura
patent: 4669043 (1987-05-01), Kaplinski
patent: 4670858 (1987-06-01), Almy
patent: 4675811 (1987-06-01), Kishi et al.
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4733348 (1988-03-01), Hiraoka et al.
patent: 4733350 (1988-03-01), Tone et al.
patent: 4747043 (1988-05-01), Rodman
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 4775955 (1988-10-01), Liu
patent: 4811203 (1989-03-01), Hamstra
patent: 4811209 (1989-03-01), Rubinstein
patent: 4812969 (1989-03-01), Takagi et al.
patent: 4819159 (1989-04-01), Shipley et al.
patent: 4827401 (1989-05-01), Hrustich et al.
patent: 4849881 (1989-07-01), Eguchi
patent: 4885680 (1989-12-01), Anthony et al.
Electronic message from Freige PA on the subject, "Abstract for Pradeep Sindhu `The Dragon Memory System`, 11-12-85," Oct. 16, 1985.
Sindhu, "The Dragon.TM. Memory System", Slides shown with talk delivered Nov. 12, 1985.
Katz, R. H. et al., "Implementing a Cache Consistency Protocol", Proceedings: 12th Annual International Symposium on Computer Architecture, Jun. 17-19, 1985, Boston, Computer Society Press, Piscataway, N.J., 1985, pp. 276-283.
Goodman, James R., "Using Cache Memory to Reduce Processor-Memory Traffic", 10th Annual International Symposium on Computer Architecture, 1983, Computer Society Press, Piscataway, N.J., 1983, pp. 124-131.
Monier, Louis et al., "The Architecture of the Dragon", delivered at IEEE 1985 Compcon, San Francisco, Spring 1985.
Koo, James T., "Integrated-Circuit Content-Addressable Memories", in Hodges, D. A., (Ed.) Semiconductor Memories, IEEE Press, New York, 1972, pp. 263-270.
Bartlett, James et al., "Associative Memory Chips: Fast, Versatile, --And Here", in Riley, W. B., (Ed.) Electronic Computer Memory Technology, McGraw-Hill, New York, 1971, pp. 217-221.
Intel Bipolar LSI Memory 3104, in Hodges, D. A., (Ed.) Semiconductor Memories, IEEE Press, New York, 1972, pp. 271-278.
McCreight, E. M., "The Dragon Computer System", Proceedings of the NATO Advanced Study Institute on Microarchitecture of VLSI Computers, Urbino, Jul. 1984, pp. 83-101.

Affiliated with

Also associated with

Rating

Multiprocessor cache memory housekeeping does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiprocessor cache memory housekeeping, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor cache memory housekeeping will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1013646