Digital data modulation circuit having a DC component suppressio

Details Digital data modulation circuit having a DC component suppressio Digital data modulation circuit having a DC component suppressio

1989-08-01

1991-08-20

Atkinson, Charles E.

Excavating

371 572, 341 58, 375 19, 375 34, H03M 700, G06F 1100

Patent

active

050420372

ABSTRACT:
In a digital data modulation circuit, a digital data block formed of k words, each of which includes m-bit binary data, is input to an error-correcting coding circuit which adds (n-k) check words to the input data block. The error-correcting coded data block is supplied to an arithmetic operation circuit, which calculates the number of "1" bits and the number of "0" bits to be included in the coded data block output from the error-correcting coding circuit so that the difference between the number of "0" bits and the number of "1" bits included in the coded data blocks which have been output from the error-correcting coding circuit approximates 0 and calculates one control word corresponding to the calculated number. The coded data block output from the error correcting coding circuit is supplied to a modulo-two adder which adds the control word to every word belonging to the coded data block.

REFERENCES:
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patent: 3840854 (1974-10-01), Franaszek
patent: 4309694 (1982-01-01), Henry
patent: 4414659 (1983-11-01), Beckers
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patent: 4688226 (1987-08-01), Burgmeier et al.
patent: 4731797 (1988-03-01), Jaffre et al.
IEEE Transactions on Magnetics, vol. mag-22, No. 5, pp. 1194-1196, S. Fukuda et al; Sep. 1986.
ITEJ Technical Report ICS 81-10, pp. 59-64, "A New DC-Suppressed Channel Coding for DPCM", M. Kashida et al.

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