Method for programming a floating gate memory device

Details Method for programming a floating gate memory device Method for programming a floating gate memory device

1988-12-09

1991-08-20

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518901, 36523001, G11C 1300

Patent

active

050420097

ABSTRACT:
A method of programming a floating gate transistor permits the use of a charge pump to provide drain programming current. The programming drain current is typically held below about 1 .mu.A. This programming drain current can be provided by a conventional charge pump. In the first embodiment, the drain current can be limited by connecting a resistor between the source and ground. In a second embodiment, the drain current is limited by limiting the transistor control gate voltage. In a third embodiment, a charge pump is coupled to the drain while the control gate is repetitively pulsed. Each time the control gate is pulsed, the transistor turns on, and although the drain is initially discharged through the transistor, some hot electrons are accelerated onto the floating gate, and eventually the floating gate is programmed. In these embodiments the erase gate voltage may be raised to enhance programming efficiency.

REFERENCES:
patent: 4580067 (1986-04-01), Proebsting et al.
patent: 4628487 (1986-12-01), Smayling
patent: 4667312 (1987-05-01), Doung et al.
patent: 4723225 (1988-02-01), Kaszubinski et al.
patent: 4763299 (1989-08-01), Hazane
R. Kazerounian, et al., "A 5 Volt Only High Density Poly-Poly Erase Flash Eprom Cell", IEDM. Dec. 1988, pp. 436-439.

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