Method of making an insulated-gate semiconductor device with imp

Details Method of making an insulated-gate semiconductor device with imp Method of making an insulated-gate semiconductor device with imp

1983-12-30

1987-02-24

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29575, 29589, 29590, 148DIG53, 148DIG106, 148DIG126, 148 15, H01L 21265

Patent

active

046446370

ABSTRACT:
An insulated-gate semiconductor device, such as an IGFET or IGT, with improved source-to-base shorts includes, in a semiconductor wafer, a drain region, a voltage-supporting region, a base region, and a source region. Generally parallel gate fingers of refractory material are insulatingly spaced above the wafer. Elongated base portions are provided between, and preferably registered to, a respective pair of adjacent gate fingers. Elongated source portions are each situated within a respective base portion and each is preferably registered to a respective pair of adjacent gate fingers. Generally parallel shorting portions are included in the wafer and are oriented transverse to the gate fingers, whereby the shorting portions can be formed without a critical alignment step. The shorting portions adjoin the base portions and also a source electrode so as to complete source-to-base electrical shorts. Parasitic majority current carriers in the base portions are readily drawn into the shorting portions, which are preferably situated very close to each other and, then, are conducted to the source electrode. Accordingly, the shorting portions are highly effective at reducing parasitic currents in the device.

REFERENCES:
patent: 3909925 (1975-10-01), Forbes et al.
patent: 4199774 (1980-04-01), Plummer
patent: 4364073 (1982-12-01), Becke et al.
patent: 4417385 (1983-11-01), Temple
patent: 4430792 (1984-02-01), Temple
Leboss, Bruce, "Power Transistors Unite MOS, Bipolar", Electronics, Apr. 21, 1981.
Specification and Drawings for SN 396,172, filed on 7 Jul. 1982, by VAK Temple.

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