VDMOS/logic integrated circuit comprising a vertical depleted MO

Details VDMOS/logic integrated circuit comprising a vertical depleted MO VDMOS/logic integrated circuit comprising a vertical depleted MO

1990-07-16

1991-09-03

Wojciechowicz, Edward J.

Fishing, trapping, and vermin destroying

357 2312, 357 13, 357 41, 437 40, 437141, 437904, 437913, H01L 2978, H01L 21265

Patent

active

050459023

ABSTRACT:
An integrated circuit comprises power elements of the enhanced vertical diffused MOS (VDMOS) transistor type (1) and logic elements of the depleted (2) and enhanced (3) lateral MOS transistor type, and further comprises an internal voltage reference resulting from the series connection of a depleted VDMOS transistor (60) having a common drain with the enhanced VDMOS transistor and a zener diode (70), the cathode of which is connected to the source of the depleted VDMOS transistor and the anode is connected to the substrate and to the gate of this depleted VDMOS transistor.

REFERENCES:
patent: 4163988 (1979-08-01), Yeh et al.
patent: 4451744 (1984-05-01), Adam
patent: 4792840 (1988-12-01), Nadd
patent: 4819044 (1989-04-01), Murakami
patent: 4862233 (1989-09-01), Matsushita et al.
patent: 4872045 (1989-10-01), Baba et al.

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