Boots – shoes – and leggings
Patent
1995-01-27
1997-10-21
Chin, Tommy P.
Boots, shoes, and leggings
386131, G06F 1710
Patent
active
056803354
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a rate converter for converting the rate of data for exchanging data between digital circuits operating at two different clock rates, and to an imaging apparatus provided with the rate converter.
BACKGROUND ART
In general, for exchanging data between two digital circuits operating at different clock rates, a rate converter is needed for converting the data rate.
For example, when exchanging digital video signals between a digital video signal processing circuit of an imager operating at a clock rate of 18 MHz and a digital video signal processing circuit of a digital video tape recorder (RVTR) operating at a clock rate of 13.5 MHz pursuant to D1 standard, a rate converter, such as a 4:3-down rate converter for converting the rate of digital video signal outputted from the imager from 18 MHz to 13.5 MHz, or a 3:4-up rate converter for converting the rate of digital video signals outputted from the DVTR from 13.5 MHz to 18 MHz, is needed.
The imager employing a solid-state imaging device usually has a clock rate determined by the number of pixels of the solid-state imaging device. For example, with an imager employing 500,000 pixel solid imaging devices, the digital video signal processing circuit operates at a clock rate of 18 MHz.
With the conventional rate converter, output data of a desired output clock rate is obtained by upconverting input data to a clock rate equal to the least common multiple of the input clock rate and the output clock rate and by thinning out via a filter. Thus the conventional rate converter is in need of filtering at the output clock rate equal to the above-mentioned least common multiple.
For example, with a 4:3-down rate converter, input data at the 18 MHz clock rate is converted by the filtering shown in FIGS. 1 and 2 into output data having the clock rate of 13.5 MHz.
That is, with the 4:3-down rate converter, zero data is inserted at the positions of 18 MHz clock rate input data {X.sub.m } shown at A in FIG. 1 which can become sampling points for 13.5 MHz as shown at B in FIG. 1 for upconverting the input data to the clock rate of a frequency equal to the least common multiple of 18 MHz and 13.5 MHz, that is 54 MHz. Thus, in the frequency domain, the frequency components repeated on the basis of 18 MHz as shown at A in FIG. 2 are now repeated at the unit of repetition of 54 MHz, with the frequency characteristics remaining unchanged, as shown at B in FIG. 2.
The 54 MHz clock rate data is then passed through a filter having characteristics shown at C in FIG. 1 and at C in FIG. 2. That is, since the output clock rate is 13.5 MHz, should there be frequency components of not less than 6.75 MHz (one-half of 13.5 MHz) up to 27 MHz (one-half of 54 MHz), aliasing is produced when the clock rate is set to 13.5 MHz, and hence original frequency characteristics cannot be maintained. Consequently, the data is passed through a low-pass filter for suppressing frequency components not less than 6.75 MHz.
The data {Y.sub.i } at the clock rate of 54 MHz having frequency components not less than 6.75 MHz suppressed, is obtained as data Y.sub.1 to Y.sub.14, that is, .multidot.X.sub.2 +k.sub.11 .multidot.X.sub.1 .multidot.X.sub.3 +k.sub.9 .multidot.X.sub.2 .multidot.X.sub.3 +k.sub.10 .multidot.X.sub.2 .multidot.X.sub.3 +k.sub.11 .multidot.X.sub.2 .multidot.X.sub.4 +k.sub.9 .multidot.X.sub.3 .multidot.X.sub.4 +k.sub.10 .multidot.X.sub.3 .multidot.X.sub.4 +k.sub.11 .multidot.X.sub.3 .multidot.X.sub.5 +k.sub.9 .multidot.X.sub.4 .multidot.X.sub.5 +k.sub.10 .multidot.X.sub.4 .multidot.X.sub.5 +k.sub.11 .multidot.X.sub.4 .multidot.X.sub.6 +k.sub.9 .multidot.X.sub.5 .multidot.X.sub.6 +k.sub.10 .multidot.X.sub.5 .multidot.X.sub.6 +k.sub.11 .multidot.X.sub.5 .multidot.X.sub.7 +k.sub.9 .multidot.X.sub.6 function represented by the formula (1) ##EQU1## using a transversal filter operating at 54 MHz, with the number of taps being 12.
From the data {Y.sub.i }, with the clock rate of 54 MHz, as shown at D in FIGS. 1 and 2, every three data of i=3n, i=3n+1 or i=3n
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John G. Proakis Et. Al. `Introduction to Digital Signal Processing` 1989, Macmillan Publishing Co., New York *paragraph 8.5.4*.
Ikeyama Hiromasa
Kihara Taku
Nohda Shigetoshi
Chin Tommy P.
Frommer William S.
Lee Y.
Sinderbrand Alvin
Sony Corporation
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